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NEC's 3 V DUAL DOWNCONVERTER AND UPB1007K PLL FREQUENCY SYNTHESIZER
FEATURES
* INTEGRATED RF BLOCK: LNA, RF & IF Downconverter + PLL frequency synthesizer * STATE OF THE ART 25 GHz fT UHS0 BIPOLAR PROCESS * DOUBLE-CONVERSION: f1stIF = 61.380 MHz f2ndIF = 4.092 MHz * ADJUSTABLE GAIN: 20 dB range MIN * FIXED DIVISION PRESCALER * LOW POWER CONSUMPTION: 25 mA @ 3 V * SMALL 36 PIN QFN PACKAGE Flat lead style for better performance * TAPE AND REEL PACKAGING AVAILABLE
DESCRIPTION
NEC's UPB1007K is a Silicon RFIC designed for low cost GPS receivers. The IC combines an LNA, followed by a doubleconversion RF/IF downconverter block and a PLL frequency synthesizer on one chip. The device operates on a 3V supply voltage and is housed in a small 36 pin QFN (Quad Flat Nolead) package, resulting in low power consumption and reduced board space. The device is manufactured using the state of the art UHS0 25 GHz fT silicon bipolar process. NEC's stringent quality assurance and test procedures ensure the highest reliability and performance.
APPLICATIONS
* LOW POWER HANDHELD GPS RECEIVER * IN-VEHICLE NAVIGATION SYSTEMS * PC/PDA+GPS INTEGRATION
ELECTRICAL CHARACTERISTICS (TA = 25C, VCC = 3.0 V, unless otherwise specified)
SYMBOLS ICC VCC PART NUMBER PACKAGE OUTLINE PARAMETERS AND CONDITIONS Total Circuit Current, No Signals Supply Voltage UNITS mA V 2.7 MIN UPB1007K QFN-36 TYP 25 3.0 MAX 31 3.3
LNA (fRFin = 1575.42 MHz, ZL = ZS = 50 ) ZLNAin RF Input Impedance of LNA 28 - j38 ZLNAop RF Output Impedance of LNA 85 - jx6 P1dBLNA 1 dB Compression, Input matched dBm -22 PGLNA Power Gain LNA, Input matched, PRFin = -60 dBm dB 14 15 NFLNA Noise Figure of LNA, Input matched dB 2.8 Mixer (fRFin = 1575.42 MHz, f1stLOin = 1636.80 MHz, PLO = -10 dBm, f1stIF = 61.38 MHz, ZL = ZS = 50 ) ZMIXin RF Input Impedance of Mixer 31 -j103 P1dBMIX 1 dB Compression (refer to input), Input matched dBm -25 PCGMIX Power Conversion Gain dB 21 NFMIX Noise Figure of Mixer (SSB), Input matched dB 9.5 ALO-IF LO Leakage to IF Pins, PLO = -10 dBm dBm -40 ALO-RF LO Leakage to RF Input Pins, PLO = -10 dBm dBm -48 ZMIXout RF Output Impedance of Mixer +152 - j9 PLL ICPOH PLL Charge Pump High Side Current @ VCPout = VCC/2 mA 1 ICPOL PLL Charge Pump Low Side Current @ VCPout = VCC/2 mA -1 fPD Phase Comparison Frequency MHz 8.184 IF Downconverter Block (f1stIFin = 61.38 MHz, f2ndLOin = 65.472 MHz, f2ndIF output = 4.092 MHz, ZS = 2k, ZL = 2 k) NF2ndMIX Noise Figure of 2nd IF Mixer (SSB), (ZS = 50) dB 12 GV2ndMIX Voltage Gain of 2nd Mixer/Amplifier, P1stIF = -50 dBm dB 47 VGC Gain Control Voltage (Voltage at maximum gain) V 0.5 DGC Gain Control Range, P1stIF = -50 dBm dB 20 (Voltage at maximum gain) A2ndLO1stIF 2nd LO Isolation to 1st IF Input Pins, VAGC = 0 V dB -70 A2ndLO2ndIF 2nd LO Isolation to 2nd IF Output Pins, VAGC = 0 V dB -70
3.2
10
California Eastern Laboratories
UPB1007K ELECTRICAL CHARACTERISTICS (TA = 25C, VCC = 3 V, unless otherwise specified)
PART NUMBER PACKAGE OUTLINE SYMBOLS PARAMETERS AND CONDITIONS UNITS MIN UPB1007K QFN-36 TYP MAX
2nd IF Amplifier Block (f2ndIF = 4.096 MHz, ZS = 2k, ZL = 2 k) ) GVLIM fBB VREFin VREFout Voltage Gain of Limiter Amplifier, PIN = -60 dBm Roll-off Frequency dB MHz mVpp Vpp V V 400 1.1 1.83 48 110 400 1.2 1.86 0.5 1.3 2.15 0.6
Reference Amplifier Block Reference Input Minimum Level Reference Output Swing (open collector output), CL = 2 pF//RL = 10 k Power Down Control Pins VIH VIL Digital Control Input High Digital Control Input Low
ABSOLUTE MAXIMUM RATINGS1,2 (TA = 25C)
SYMBOLS VCC PT TOP TSTG PARAMETERS Supply Voltage Total Power Dissipation3 Operating Temperature Storage Temperature UNITS V mW C C RATINGS 3.6 433 -40 to +85 -55 to +150
RECOMMENDED OPERATING CONDITIONS
SYMBOLS VCC TOP fRFin fREFin fREFout f1stLO f1stIFin f2ndLOin f2ndIFin f2ndIFout VIH PARAMETERS Supply Voltage Operating Temperature RF Input Frequency Reference Frequency 1st LO Oscillating Frequency 1st IF Input Frequency 2nd IF Input/Output Frequency Power Down Control Voltage "High" Power Down Control Voltage "Low" UNITS MIN V C MHz MHz 2.7 -40 TYP 3.0 +25 1575.42 16.368 MAX 3.3 +85
Notes: 1. Operation in excess of any one of these parameters may result in permanent damage. 2. More than two items must not be reached simultaneously. 3. TA = +85C, mounted on a 50 x 50 x 1.6 mm double-sided copper clad epoxy glass PWB.
MHz MHz
1636.8 61.38 65.472 4.092 1.8 3
2nd LO Input Frequency MHz MHz V
VIL
V
0.6
UPB1007K CURRENT BUDGET
SYMBOL VCC ICC ICC_PL ICC_XO ICC_RX ICC_LNA ICC_MIX1 ICC_MIX2 ICC_IFAMP ICC_XO ICC9 ICC_CF VIL VIH PARAMETER AND CONDITIONS Supply Voltage Total Circuit Current, VCC = 3.0 V, no signal Power Down Node Current Oscillator Supply Current, (Pin 15 = 0 V, Pin 16 = 3 V) Receiver Supply Current, (Pin 15 = 0 V, Pin 16 = 3 V) Supply Current of LNA, RF off Supply Current of RF Mixer, RF off Supply Current of IF Mixer, RF off Supply Current of IF Amplifier, RF off Crystal Oscillator Supply Current PLL Supply Current Control Functions Supply Current Power Down Pin Logic LOW Level Power Down Pin Logic HIGH Level Power-on Response Time UNITS V mA mA mA mA mA mA mA mA mA mA A V V ms 1.8 3 MIN 2.7 TYP 3.0 25 0.15 2.7 22.3 2.6 6.7 3.5 1.1 2.7 6.3 2.1 0.6 MAX 3.3 31 IC Performance Parameters
Functional Blocks Current Details
d_PON
APPLICATION EXAMPLE
1575.42 MHz
BASEBAND
25
8
PD
2
LOOP FILTER TUNING ELEMENT REFERENCE FREQ.
IC
UPB1007K PIN FUNCTIONS
Pin No. Symbol Function and Application Internal Equivalent Circuit
1
LNAout
Output pin of LNA. Output biasing and matching required as it is an open collector output. Supply voltage pin of regulator mixer block. Ground pin of regulator reference cell.
2 3
VCC (Vreg) GND (Vreg)
4
RF MIXin
Input pin of RF mixer. 1575.42 MHz band pass filter can be inserted between pin 1 and mixer input.
5 6 7
GND (MIX) 1stLO-OSC1 1stLO-OSC2
Ground pin of RF mixer cell. Pins 6 & 7 are base pins of the differential amplifier for 1st LO oscillator. These pins should be equipped with LC and varactor circuits to oscillate at 1636.8 MHz.
8
VCC (1stLO-OSC)
Supply voltage pin of differential amplifier for 1st LO oscillator circuit (VCO).
9
VCC (Charge Pump) PD-out
Supply voltage pin of the phase detector charge pump. This is a current mode charge pump output for connection to a passive RC loop filter for driving the external varactor diode of 1stLO-OSC. Ground pin of phase detector charge pump.
10
11
GND (Charge Pump)
UPB1007K PIN FUNCTIONS
Pin No. Symbol Function and Application Internal Equivalent Circuit
12
VCC (Divider Block)
Supply voltage pin of prescaler, phase detector, crystal oscillator, VCO buffer.
13
LO_out
Monitor pin of frequency at phase detector.
14
XO_out
Monitor pin of oscillator /2 output at phase detector.
15
PD1
Power down control pin Low = Whole chip off except XTAL osc. High = Whole chip on except XTAL osc.
16
PD2
Reference block standby mode. Low = Reference block disabled. High = Reference block enabled.
17
REFout
Output pin of reference frequency. The frequency from pin 17 can be taken out as 1Vp-p swing.
UPB1007K PIN FUNCTIONS
Pin No. Symbol Function and Application Internal Equivalent Circuit
18
REF gnd
Differential oscillator input. This pin should be grounded via a capacitor. Input pin of the reference frequency buffer. This pin should be equipped with an external 16.368 MHz oscillator (e.g. TCXO).
19
REFin
20
VCC (Ref Block) GND (Ref Block) 2nd IFout
Supply voltage pin of output charge pump of the oscillator. Ground pin of the oscillator, prescaler, phase detector and VCO. Output pin of 2nd IF amplifier. This pin output 4.092 MHz clipped sinewave. This pin should be equipped with external inverter to adjust level to next stage on user's system. Supply voltage pin of 2ndIF amplifier Bypass pin of 2nd IF amplifier input. This pin should be grounded via a capacitor. Pin 1 of 2nd IF amplifier input . 2nd IF filter can be inserted between 25 & 28. Pin 2 of 2nd IF amplifier input. This pin should be grounded via a capacitor. Ground pin of 2nd IF amplifier.
21
22
23
VCC 2ndIFAMP 2ndIF bypass
24
25
2ndIFin1
26
2ndIFin2
27
GND (2ndIF AMP) IF MIXout
28
Output pin from IF mixer. IF mixer output signal goes through gain control amplifier before this emitter follower output port.
29
VCC (IF MIX)
Supply voltage pin of IF mixer, gain control amplifier.
UPB1007K PIN FUNCTIONS
Pin No. Symbol Function and Application Internal Equivalent Circuit
30
VGC (IF MIX)
Gain control voltage pin of IF mixer output amplifier. This voltage performs forward control, i.e., (VGC upGain down).
31
IF-MIXin
Input pin of IF mixer and IF VAGC.
32
GND (IF-MIX)
Ground pin of IF mixer and IF VAGC.
33
RF-MIXout
Output pin of RF mixer . 1st IF filter must be inserted between pins 31 and 33.
34
VCC (RF-MIX)
Supply voltage pin of RF mixer block. This pin must be decoupled with capacitor (e.g. 1000 pF).
35
LNAin
Input pin of low noise amplifier. Optimal input matching required for low noise performance. Ground pin of LNA.
See Pins 1-3
36
GND (LNA)
UPB1007K
INTERNAL BLOCK DIAGRAM
33 RF-MIXout 28 IF-MIXout VCC 34 (RF-MIX) 31 IF-MIXin VGC 30 (IF-MIX) GND (IF-MIX) 35 LNAin VCC (IF-MIX) 29 GND (LNA) 36
32
LNAout VCC (Vreg) GND (Vreg) RF-MIXin GND (MIX/LO) 1stLO-OSC1 1stLO-OSC2 VCC (1stLO-OSC1) VCC (charge pump)
1 2 3 4 5 6 7 8 9
PD Vreg
27 26 25 24 23 22
GND (2ndIF-Amp) 2ndIFin1 2ndIFin2 2ndIFbypass VCC (2ndIF-Amp) 2ndIFout
/25 /8 /2
21 GND (Div & Ref Block) 20 19 VCC (Ref Block) REFin
Pres_LOout 13
XO_out 14
Power Down 1 15 (whole chip)
Power Down 2 16 (Ref Block)
REFout 17
PDout 10
ORDERING INFORMATION
Part Number UPB1007K Package 36 Pin plastic QFN
GND 11 (charge pump)
VCC (divider block) 12
OUTLINE DIMENSIONS (Units in mm)
Package Outline QFN-361
6.20.2 6.00.2
6.00.2
Package Outline QFN-36
Pin 36
6.4 6.0
Pin 1
3.8 0.5
6.20.2
6.20.2
6.00.2
ACTUAL SIZE (Units in mm)
REF gnd 18
4 -CO.5
0.220.05 0.550.2
6.00.2 0.14+0.10 -0.05
Note: 0.50.025 1. The solder pads on each corner should be grounded.
Life Support Applications These NEC products are not intended for use in life support devices, appliances, or systems where the malfunction of these products can reasonably be expected to result in personal injury. The customers of CEL using or selling these products for use in such applications do so at their own risk and agree to fully indemnify CEL for all damages resulting from such improper use or sale.
1.0 MAX
6.20.2
02/28/2003
A Business Partner of NEC Compound Semiconductor Devices, Ltd.

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